The present invention relates to an apparatus and method of manufacture for wafer probe station systems and the use of guarding and shielding systems for limiting electrical leakage currents and noise. More particularly, the invention relates to approaches for providing a chuck apparatus system which facilitates guarding and shielding techniques for improving the accuracy of low current and low voltage measurements of a device-under-test (DUT), typically a wafer containing one or more integrated circuits.
Modern wafer probe stations have been developed for making accurate low voltage and low current measurements of semiconductor integrated circuit wafers and other electronic component applications. Wafer probe stations having a guarding system have been developed for reducing current leakage, with Kelvin connection systems and the like to eliminate voltage losses associated with conductive line resistances, and electromagnetic interference (EMI) shielding elements for minimizing the effects of parasitic capacitance and noise in the test environment. The technique of guarding to minimize current leakage during low current measurements, the use of Kelvin connections for low voltage measurements, and the provision of EMI shielding portions are well known and discussed extensively in the technical literature. In guarding applications, in particular, an isolated conductor surrounding or otherwise positioned closely adjacent to low current circuitry, and maintained at the same or nearly the same potential provided as the low current circuit conductors, reduces leakage currents such that the low current measurements may be made accurately. In shielding applications, conductive material connected to ground potential reduce the effects of EMI from external and probe station electronics and other noise on test measurements.
The need to observe device behavior with very low level current and voltage measurements is being driven by the ongoing reduction in the integrated circuit semiconductor device geometry in order to increase circuit density, facilitate higher speeds, and reduce power consumption. Decreasing the scale of the circuit can provide the aforementioned improvements, however, tradeoffs in performance may also occur. A number of factors can adversely affect low level voltage and current measurements, including, impedances in which an impedance or current path unintentionally shares a noise source or other instrumentation, the transfer of a noise voltage through usually coupled incidental inductances, magnetically coupled noise, incidental capacitive coupling, charge transfer due to the proximity of charge bodies to the test circuitry, and the like. These mechanisms often perturb measurements taken in integrated circuit devices requiring very low level measurements. The measurement of current values in the high attoampere and the low femtoampere regime is particularly difficult in the presence of interfering sources that may be capable of generating current flow of electrons which, though minuscule, may be substantial relative to the very low voltage and low currents being measured.
In one known approach to providing a guarded and shielded chuck assembly, the assembly includes multiple conductive chuck elements spaced vertically and electrically insulated from each other. The upper chuck element supports the test wafer, and a conductive ring mechanically attached to one of the lower chuck elements surrounds the outer periphery of the chuck assembly to serve as a guard element. In such known assembly, an annular air gap between the chuck assembly elements and the surrounding guard ring serves as a dielectric to isolate the guard ring from the conductive wafer support element. A dielectric material may also be present in the annular gap. The size of the annular space provided in such a design directly affects its dielectric properties and capacitance, and in turn the degree of isolation from the support surface on which testing occurs. However, maintaining the desired registration between the chuck elements and the guard ring in such a design may be difficult. Even slight offsets in the associated mechanical connections between the various elements or in the shape of the guard ring can affect the registration and detrimentally alter the performance of the chuck.
Another known approach involves use of a chuck assembly in which the wafer support layer is a first conductive material sputtered on the upper surface of an insulator element, which in turn rests atop a second conductive chuck element. An electrically isolated dish has a bottom portion which extends laterally below the second conductive element, and an annular side wall which extends around the outer periphery of the chuck assembly and terminates vertically opposite the insulator element. The dish may be connected as a shield and the second conductive element as a guard. Such an approach may be suitable in certain applications, but does not provide significant guarding around the side periphery of the conductive support surface and the location of testing. In addition, with the annular side wall of the shield opposing the metal sputtered insulator element, parasitic and parallel capacitance may occur between the shield and the conductive test surface and distort test measurements.
It would be desirable therefore to provide an integrated approach to guard and shield systems of wafer probe stations designed to accommodate low level current and voltage measurements with sensitivities in the high attoampere and the low femtoampere regime, which is not easily feasible with presently known designs of guarding systems or shielding systems in commercial probe stations. The shield and guard system should provide electrical isolation as well as for the reduction of parasitic capacitance and noise experienced by the device under test at the conductive test surface. Excessive hysteresis associated with built up electrical charge at the test surface should also be minimized to reduce the time required for stabilizing measurement voltages to the device under test.
Measurements of low level currents in the high attoampere and low femtoampere regime are particularly susceptible to errors induced by capacitive loading, electrical discharge, and noise events which occur because of the dielectric characteristics of nonconductors in and surrounding the conductive test surface, which effects may significantly distort measurement values and limit the accuracy of low voltage and low current measurements. Poor tester and prober grounding or poorly insulated or guarded probes will contribute to electrical noise from power supplies or external circuits which may enter the probing environment and be coupled to the measurements. Additionally, offsets and drifting associated with parasitic capacitances may result in hysteresis of the current and voltage measurements producing erroneous data offsets, inaccuracies, and long measurement times. Advantageously, it would be desirable to provide an integrated approach which brings the overall wafer probe station and chuck design into cooperative relationship for both guarding and shielding for the reduction of parasitics and noise and which also minimizes the effects of capacitance in the overall system.